An apparatus for analyzing defective memory cells of a memory of semiconductor devices fabricated as integrated circuits to determine a way to efficiently repair the defective memory cells using spare memory cells is called the MRA (Memory Repair Analyzer). The semiconductor devices are not limited to dedicated memory devices; they may be any semiconductor devices containing memory devices. Semiconductor devices to which the present invention is applied will be hereinafter referred to as memory devices and a memory device to be tested will be referred to as a DUT (Device Under Test). There are a number of MRA approaches. One typical example will be described below.
FIG. 8A shows a wafer 110 on which a large number of semiconductor devices are formed in an array. MRA is performed in the stage preceding a memory test, that is, it is performed in an on-wafer stage. A large number of memory devices are formed in an array on the wafer 110. Each of the memory devices has multiple memory blocks, each consisting of many memory cells. As a memory block 120 is schematically shown in FIG. 8B, more than one spare lines 130, 135 are provided for each memory block 120 along the rows (in the X-axis direction) and the columns (in the Y-axis direction).
Here, suppose that a test on the memory block 120 revealed that memory cells 122, 125, and 127 are defective. The test result data can be analyzed using MRA to determine a repair solution. FIG. 8C shows a repair solution in which the column line 131 of a memory cell 122 is replaced with one of the column spare lines 130 and the row line 136 of memory cells 125 and 127 is replaced with one of the row spare lines 135 by the MRA. Such repair of defective cells of memory devices formed on a wafer is described in U.S. Pat. No. 6,345,004 and U.S. Pat. No. 6,243,307, for example.
The MRA is means capable of analyzing fast which spare line a defective memory cell found in a memory device can be replaced with to repair the defect, by using dedicated hardware and software. The MRA has been sufficiently effective for repairing conventional memory ICs.
Memory devices have made remarkable progress in recent years. With the advent of 64M-SDRAM, more and more memory devices have unique redundancy structures specified by users (LSI manufactures) and have become complicated. As a result, a problem has arisen that the result of MRA analysis must be adjusted through a post process (post process at an on-wafer stage) as will be described later. That is, the conventional MRA capabilities are used to obtain a repair solution and then an engineering work station (EWS) must be used in a post process to make adjustments to the solution.
However, because this method can adjust only one solution determined by the MRA, it has been impossible for a post process to determine whether there is a solution that makes a defect found to be unrepairable as a result of adjustments in the post process repairable. Consequently, the yields have been reduced. An example of a device that could not be repaired using conventional MRA because of a redundancy structure will be described below.
The memory device shown in FIG. 9 consists of four block groups BG1-BG4. Block groups BG1 and BG2 make up BANK-A and block groups BG3 and BG4 make up BANK-B. Each block group consists of four blocks. Two spare row lines 135 are provided in each bank for repairing two block groups at a time. Two column spare lines 130 are provided for each block. The following three conditions are required to assign spare lines for repair of a defective memory cell.
FIG. 10 illustrates a first condition. The two spare lines in each block can repair any defective cells in the same block group freely in principle, with some exceptions.
FIG. 11 illustrates a second condition. The second condition is an exception to the first condition. The spare line of the rightmost block BL4 in the same block group cannot repair defective cells in the leftmost block BL1. Similarly, the spare lines of the leftmost block BL1 cannot repair defective cells in the rightmost block BL4.
FIG. 12 illustrates a third condition. This condition is as follows. Consider two adjacent blocks in two adjacent block groups, for example block BL4 in block group BG3 and block BL5 in block group BG4, in the same bank. If fails at address “a” that have occurred in block BL4 are repaired with a spare line of block BL4, fails at the same address “a” in the adjacent block BL5 cannot be repaired with a spare line of block BL5. However, address “a” in block BL5 can be repaired with a spare line of adjacent block BL6.
The example shown in FIG. 9 is of a memory device having three constrains of a redundancy structure. There are many other memory devices having various structures. It has become impossible to repair all of the various types of memory devices with conventional MRA. For example, the conventional MRA can address the first and second conditions in the memory device in FIG. 9, but not the third condition.
As has been stated above, the first and second conditions in the memory device having the redundancy structure shown in FIG. 9 can be addressed with the conventional MRA. After the MRA is performed, a post process must be performed for checking the third condition on the EWS to adjust the result of the repair. In addition, since only one repair solution of the first and second conditions is obtained before the third condition is checked, an optimum solution cannot necessarily be obtained and, consequently, a reduction in the yield can result.
That is, for the example described above, the conventional MRA requires, as the conceptual diagram shown in FIG. 13, performing a function test on a DUT (step S140), performing memory repair analysis (MRA) by inputting data on the results of the test to obtain a repair solution under the restrictions of the first and second conditions (step S141), storing temporarily the repair solution (step S142), and making adjustments to the result and the third condition on the EWS (step S143) to obtain a final repair solution.
An object of the present invention is to provide a semiconductor device test apparatus and method capable of analyzing and repairing the first, second, and third conditions at a time using a general-purpose MRA.